1. Field of The Invention
The present invention relates generally to a device formed on a semiconductor substrate. More specifically, the invention relates to a semiconductor device having both of low-voltage and high-voltage peripheral circuits. As semiconductor devices having both of low-voltage and high-voltage peripheral circuits, there are electrically rewritable non-volatile semiconductor devices (EEPROMs), and consolidated LSIs wherein an EEPROM and another memory or a logic LSI are consolidated. The invention also relates to a semiconductor device, such as an EEPROM which has simultaneously formed cell gate and peripheral gate contact and wherein the area of the peripheral gate contact is intended to reduce. In addition, the invention relates to a semiconductor device, such as an EEPROM wherein the area of a contact in a select gate electrode is intended to reduce. Moreover, the invention relates to a method for producing the semiconductor device.
2. Related Background Art
Of semiconductor devices, electrically rewritable non-volatile semiconductor memory devices (EEPROMs) require a voltage of about 10 to 20 V in order to carry out a writing or erasing operation. In addition, an interface and logic part of such devices are driven by a voltage of, e.g., 2 to 3 V. In such devices, a circuit for handling a high voltage of 10 to 20 V, and a circuit for handling a low voltage of 2 to 3 V are consolidated on the same chip. Because high-voltage and low-voltage transistors can not generally cope with both withstand voltage and driving capacity. In addition, this is the same in the case of a chip wherein an EEPROM and a DRAM or a logic LSI are consolidated.
Each of memory cells of an EEPROM has a charge storage layer which is formed via an insulating film on the surface of a substrate, and a control gate which is formed via an insulating film. An example of a memory cell structure of an EEPROM is shown in FIG. 34. The memory cell of FIG. 34 is provided with a floating gate electrode FGE as a charge storage layer via an insulating film IF which is formed on the surface of a substrate SS. Moreover, a control gate electrode CGF is provided via an insulating film IF which is formed on the surface of the floating gate electrode FGE.
Data are written and erased by the entrance and exit of electrons into and from the floating gate electrode FGE, so that the threshold voltage of a transistor fluctuates.
If a voltage of 0 V is applied to a p-type well and source/drain of a selected memory cell and if a write voltage Vpp(=about 20 V) is applied to a control gate CG, a high voltage is applied between the floating gate electrode FGE and the substrate SS. Then, electrons are injected from the p-type well into a floating gate FG via an FN tunnel by a tunnel current, so that the threshold voltage moves in a positive direction.
On the other hand, if a voltage of vppe(=about 20 V) is applied to the p-type well and the source/drain and if a voltage of 0 V is applied to the control gate, electrons in the floating gate are emitted into the p-type well, so that the threshold voltage moves in a negative direction.
In the above described method, the FN tunnel current using the whole surface of a channel is utilized for the entrance and exit of electrons. As other methods, there are known a method for utilizing an FN tunnel current between the diffusion layer and gate of a transistor, and a method for utilizing the hot electron injection. In either case, a relatively high voltage (about 10 to 20 V) is necessary for write or erase.
A typical peripheral circuit for operating such an EEPROM comprises a MOS transistor. The peripheral circuit for the EEPROM is roughly divided into two kinds of transistors which include a high-voltage transistor and a low-voltage transistor.
The high-voltage transistor is used in a circuit for generating a relatively high voltage (about 10 to 20 V) necessary for write or erase and for applying the voltage to memory cells. The gate oxide film thereof has a thickness of, e.g., 40 nm, so as not to be broken at the high voltage. In order to increase a withstand voltage to a break down voltage in a p-n junction and so forth, the high-voltage transistor is designed so that the distance between a source-drain contact and an element isolating region and the distance between the contact and a gate electrode are long and so that the impurity density of a source/drain diffusion layer is low.
On the other hand, the low-voltage transistor is used in a circuit, to which no high voltage is applied. In order to increase the driving force, the thickness of the gate oxide film of the low-voltage transistor is designed to be smaller than that of the high-voltage transistor. In addition, the low-voltage transistor is designed so that the distance between a source-drain contact and an element isolating region and the distance between the contact and a gate electrode are smaller than those of the high-voltage transistor and so that that the impurity density of a source/drain diffusion layer is higher than that of the high-voltage transistor.
A conventional EEPROM comprising a memory cell array, a high-voltage transistor and a low-voltage transistor as described above is shown in plan views of FIGS. 37(a) through 37(d). FIGS. 38(a) through 38(d) and FIGS. 39(a) through 39(d) are sectional views taken along lines Axe2x80x94Axe2x80x2 and Bxe2x80x94Bxe2x80x2 of FIGS. 37(a) through 37(d), respectively. The peripheral circuit of this EEPROM comprises a low-voltage NMOS, a low-voltage PMOS and a high-voltage NMOS.
A conventional method for producing the semiconductor device shown in FIGS. 37(a) through 37(d) will be described below.
FIGS. 40(a) through 46(d) are plan views showing the producing method. In addition, FIGS. 47(a) through 53(d) and FIGS. 54 through 60 are sectional views taken along lines Axe2x80x94Axe2x80x2 and Bxe2x80x94Bxe2x80x2 of FIGS. 40(a) through 46(b), respectively.
First, particularly as can be seen from FIG. 47(a) through 47(d), an element region EA defined by an element isolating region AIA is formed on a silicon substrate (a semiconductor substrate) SS. Moreover, a gate electrode GE is formed on the element region EA via a gate insulating film GIF. Then, an impurity diffusion layer, which is to be a source/drain diffusion layer, is formed to form a MOS transistor. Then, the surface of the substrate SS is covered with an interlayer insulating film IIF. Thus, the structure shown in FIGS. 40(a) through 40(d), FIGS. 47(a) through 47(d) and FIG. 54 is obtained.
Then, as shown in FIGS. 41(a) through 41(d), FIGS. 48(l) through 48(d) and FIG. 55, a contact hole CH is formed in the source/drain diffusion layer DL of the memory cell part.
Subsequently, as shown in FIGS. 42(a) through 42(d), FIGS. 49(a) through 49(d) and FIG. 56, a polycrystalline silicon film, in which, e.g., phosphorus, is doped, is embedded in the contact hole CH.
Then, as shown in FIGS. 43(a) through 43(d), FIGS. 50(a) through 50(d) and FIG. 57, a contact hole CH is formed in the source/drain diffusion layer DL of each of low-voltage and high-voltage transistors.
Then, in order to decrease the contact resistance of the contact with the substrate SS, additional impurity ions are injected into the source/drain diffusion layer DL on the bottom of the contact. FIGS. 44(a) through 44(d), FIGS. 51(a) through 51(d) and FIG. 58 show steps of injecting additional n-type ions. That is, the contact hole of the PMOS is covered with a resist PR by the photolithography, to carry out patterning so that the contact hole CH of the NMOS is exposed, and n-type impurity ions are injected.
Thereafter, the resist PR is removed, and additional p-type impurity ions pI are injected as shown in FIGS. 45(a) through 45(d), FIGS. 52(a) through 52(d) and FIG. 59. The contact hole CH of the NMOS is covered with the resist PR, and the resist PR is patterned so that the contact hole CH of the PMOS. Thereafter, the resist PR is removed, and annealing is carried out to activate the ion-implanted impurity. Subsequently, as shown in FIGS. 46(a) through 46(d), FIGS. 53(a) through 53(d) and FIG. 60, the respective contact holes CH are filled with a metal, such as tungsten or aluminum.
Then, a metal wiring MW is formed to complete a semiconductor device shown in FIGS. 37(a) through 37(d), FIGS. 38(a) through 38(d) and FIG. 39.
In the above described producing method, a phosphorus doped polycrystalline silicon film or an amorphous silicon film is used as a filled material for a bit line contact of the cell array part. The reason for this is as follows.
In this example, as shown in FIG. 37(d), a bit line contact BLC is laid out so as to have little margin with respect to the element region EA, in order to reduce the area of the cell array as small as possible. FIG. 38(d) shows the structure wherein alignment is not shifted. However, since the contact hole CH of the bit line contact BLC is actually formed by etching the interlayer insulating film IIF after patterning by the photolithography, the dispersion in the process causes the alignment shift of the contact and the variation in contact diameter. An example of an alignment shift of a contact is shown in FIGS. 35(a) and 35(b). FIG. 35(a) is a sectional view taken along line Axe2x80x94Axe2x80x2 of FIG. 35(b). In this example, the position of the contact hole CH projects from the element region EA into the element isolating region EIA by an alignment shift t. As a result, when the contact hole CH is etched, the insulating film embedded in the element isolating region EIA is also etched, so that the side wall portion of the element region EA underlying the source/drain diffusion layer is exposed to the bottom of the contact hole. If a metal, such as tungsten or aluminum, is filled in the contact hole in this state, a short-circuit is established between the wiring and the p-type well in the side wall portion of the element region wherein the source/drain diffusion layer is not formed, so that malfunction is caused.
On the other hand, when the phosphorus doped polycrystalline silicon film or amorphous silicon film is embedded in the contact hole, even if the side wall of the element region is exposed, phosphorus is diffused into the p-type well from the embedded polycrystalline silicon film or amorphous silicon film to form a p-n junction. Therefore, the short-circuit between the wiring and the p-type well is not established. This state is shown in FIGS. 35(c) and 35(d). FIG. 35(c) is a sectional view taken along line Axe2x80x94Axe2x80x2 of FIG. 35(d).
In addition, if the contact portion of the peripheral transistor part has a parasitic resistance, the current flowing therethrough decreases to decrease the operating speed, so that the resistance of the contact portion must be lower. Therefore, the metal, such as tungsten or aluminum, which has a lower resistance than that of the polycrystalline silicon film, is used as the filled material.
When the metal is filled in the contact hole, the resistance of the junction formed between the metal and the semiconductor substrate is high unless the impurity density of the bottom of the contact is sufficiently high. Therefore, it is required to carry out the additional ion implantation to increase the impurity density to reduce the influence of the potential barrier.
Then, the problems of the semiconductor device produced by the above described producing method will be described below.
As described above, after the additional ion implantation is carried out from the contact hole, annealing is carried out to activate the injected impurity.
The interlayer insulating film is typically made of a material, the flowability of which increases when being heated. The interlayer insulating film is formed of, e.g., a BPSG film. Such an insulating film can not be sufficiently embedded in a narrow space, such as a space between gate electrodes, by only depositing the insulating film. Thereafter, a heat treatment is carried out at a temperature of, e.g., about 800 to 900xc2x0 C., to increase the flowability of the film to embed the interlayer insulating film into the narrow space.
FIG. 36(a) shows a state that a contact hole CH is formed. Thereafter, as shown in FIG. 36(b), an additional ion implantation is carried out. Thereafter, annealing is carried out to activate the ion-implanted impurity. This annealing fluidizes the interlayer insulating film IIF around the contact hole to bend the contact hole as shown in FIG. 36(c), so that there is some possibility of causing malfunction. That is, if the contact hole is bent, it is difficult to completely fill the metal, so that wiring open and leak are caused.
The space between gate electrodes decreases with the scale down of elements, so that it is required to use an interlayer insulating film having a higher flowability in order to embed the interlayer insulating film in the space. Then, the problem that the contact is bent becomes obvious.
In order to solve the above described problem, it is required that the impurity density of the source/drain diffusion layer is previously sufficiently high, in order to prevent the contact resistance between the filled metal and the substrate in the contact portion from increasing even if the additional ion implantation into the source/drain diffusion layer and the annealing for activating the impurity are stopped.
However, if the impurity density of the source/drain diffusion layer is increased, the breakdown withstand voltage of the p-n junction and the source-to-drain withstand voltage of the transistor decrease. In particular, it is difficult to ensure a withstand voltage of, e.g., 20 V or higher, which is necessary for the high-voltage transistor.
From the point of view which is slightly different from the foregoing, the prior art will be described below.
As one of non-volatile semiconductor memories, there is known a NAND type flash EEPROM having a memory cell array part which is shown in, e.g., FIG. 64. The memory cell array part of the NAND type flash EEPROM comprises a plurality of NAND cell units NCN. Each of the NAND cell units has a NAND column which comprises a plurality of (e.g., 16) memory cells connected in series, a source-side select gate transistor which is connected between one end of the NAND column and a source line SL, and a drain-side select gate transistor which is connected between the other end of the NAND column and a bit line BLi.
Each of the memory cells comprises a floating gate electrode FG, control gate electrodes (word lines) CG0 through CG15, and an n-type diffusion layer. The select gate transistor contacts a silicon-substrate-side gate electrode of a double-layer gate structure, i.e., a gate electrode which is formed in the same layer as the floating gate electrode layer of the memory cell, to function as a transistor. The select gate electrode contacts the wiring on the upper layer at a plurality of places (one place every hundreds bit lines).
The contact for the select gate electrode is formed of a barrier metal (comprising, e.g., titanium nitride and titanium) and a metal (e.g., tungsten), similar to the contact for the gate electrode of the transistor constituting the peripheral circuit. On the other hand, if the contact for connecting the diffusion layer on one end of the NAND column to the source line SL, and the contact for connecting the diffusion layer on the other end of the NAND column to the bit line BLi are formed of a barrier metal and a metal, there is some possibility that the barrier metal is not completely filled by the alignment shift so that conducting failure is caused. Therefore, these contacts are made of a polysilicon containing an n-type impurity.
There is an advantage in that the contact of the barrier metal and the metal has a smaller resistance than that of the contact of the polysilicon. However, if the alignment shift between the contact hole and the contact region of the gate electrode is caused, there is some possibility that the barrier metal is not completely filled. Therefore, it is required to take a sufficient alignment margin for the photolithography between the contact hole and the contact region of the gate electrode.
Referring to the accompanying drawings, the above described contact region of the conventional select gate electrode will be described below.
FIG. 78 is a plan view of a contact region (a region XS in FIG. 77) of the source-side select gate electrode. The area of the contact region S1 is determined in view of the alignment shift between a double-layer gate pattern S2 of a select gate electrode and a contact hole SC in the gate electrode. As shown in FIG. 78, it is assumed that the alignment shift between S1 and S2 is a, the alignment shift between SC and S1 is b, the alignment shift between SC and S2 is c (it is also assumed that the alignment shift between the contact hole in the source diffusion layer and S2 is c), the gate length of the select gate electrode is g, the minimum width capable of being worked by the photolithography process is n (the distance between the control gate electrodes is set to be n), the distance between S1 and the control gate electrode is m, the diameter of the contact hole in the gate electrode is R, and the diameter of the contact hole in the source diffusion layer is R. In this case, in order to electrically separate S1 from the control gate electrode, m must be (a+n) or higher. The minimum value of the distance between the facing CG15 and CG15 on both sides of the contact region S1 may be (2 n+2g+2c+R) if the contact region S1 does not exist, but it is (2m+2b+R) if the contact region S1 is considered. Usually, (2m+2b+R) is greater than (2n+2g+2c+R) because of limitations of alignment shifts of m and b, so that the distance 1 between the select gate electrode SGS and the control gate electrode CG15 must be greater than n. This causes problems when the area of the cell array region is reduced.
As can be seen from the foregoing, in the conventional semiconductor device having both of low-voltage and high-voltage circuits, there is a disadvantage in that the contact is bent. In addition, in the conventional non-volatile semiconductor memory having the double-layer gate structure, there is a disadvantage in that the contact region is large with respect to the contact portion of the select gate. Moreover, in such a memory device, it is an important request that the area of the contact portion is reduced with respect to the peripheral gate contact.
In addition, in order to realize a high-density NAND type flash memory device at low costs, it is naturally required to scale down a memory cell transistor having a double-layer gate electrode structure of a floating gate electrode and a control gate electrode, and it is also required to realize the scale down of a peripheral transistor having no floating gate electrode at low costs.
Therefore, as shown in FIGS. 84(a) and 84(b), as a conventional applied example of part of peripheral transistors, there is an example wherein the electrode material of a floating gate constituting a memory cell transistor is utilized as a gate electrode material of the peripheral transistors.
In this example, part of peripheral transistors are formed as follows. That is, a part of the electrode material of a control gate constituting a memory cell transistor is peeled off and removed to expose a floating gate electrode. A contact hole 113 is formed in this region, and an electrode material is filled therein. That is, the floating gate electrode material constituting a memory cell transistor is utilized as the gate electrode of the peripheral transistors.
If the peripheral transistor is thus formed, the electrode material of the gate constituting the peripheral transistor is formed of the material of a part of the memory cell transistor, so that it can be clearly seen that the number of steps of the producing process is decreased to reduce the costs. However, it is not possible to avoid the fact that a factor of inhibiting densification remains as follows.
That is, in order to form a contact hole 113 in a gate electrode constituting a peripheral transistor, it is required to provide an alignment shift margin 115 between a wiring pattern of a gate electrode and the contact hole 113, an alignment shift margin 114 between an exposed floating gate electrode material 104 and the contact hole 113, and an alignment margin 116 between the exposed floating gate electrode material 104 and a source/drain diffusion layer 109 constituting a transistor. Each of these margins will be described. First, the alignment margin 114 will be considered. If the margin 114 is not ensured, a contact hole intended region is small. Therefore, the variation in contact resistance is not only caused, but it is also possible to ensure an ohmic characteristic necessary for a gate electrode wiring. In addition, although a protective (BPSG) film 110 is etched and removed when a contact hole is formed, a field oxide film 102 provided for element isolation has no etching selectivity since it is made of SiO2 similar to the BPSG film 110. Thus, if an alignment shift is caused between the contact hole 113 and an exposed gate electrode material, the field oxide film directly underlying the contact hole 113 is etched. Therefore, the wiring layer embedded in the contact hole is not only cut due to an abrupt difference in level of an underlayer, but a silicon substrate 101 and the gate electrode 104 are sometimes electrically short-circuited. From these points of view, it is not possible to avoid decreasing yields and reliability.
Then, the alignment margin 115 will be considered. If the margin 115 is not sufficiently ensured, the contact hole intended region is small similar to the alignment margin 114. Therefore, the variation in contact resistance is not only caused, but it is also possible to ensure an ohmic characteristic necessary for a gate electrode wiring. In addition, as a difference in level of an underlayer directly below the contact hole, there is a difference in level between the thickness of the film of a control gate electrode material 106 constituting the memory cell transistor and the thickness of the film of a control gate electrode material 107 which is used as an etching mask for the electrode material of the control gate, so that it is not possible to prevent a wiring layer, which is embedded in the contact hole, from being cut due to the difference in level.
Then, the alignment margin 116 will be considered. If the margin 116 is not sufficiently ensured, when the gate electrode material 104, which is ensured so as to be sufficiently widely ensured, reaches the channel portion of the transistor due to an alignment shift, the effective width of the gate is not only reduced, but the characteristics of the transistor also vary in accordance with the alignment directions.
As described above, in the conventional example shown in FIG. 6, the three alignment shift margins 114, 115 and 116 must be ensured. This has harmful effects on the enhancement of the density of the element, and causes the increase of the area of the chip.
The alignment shift margin 115 between the wiring layer pattern 107 of the gate electrode and the contact hole 113, the alignment shift margin 114 between the exposed floating gate electrode material 104 and the contact hole 113, and the alignment margin 116 between the exposed floating gate electrode material 104 and the source/drain diffusion layer 109 constituting the transistor, which are disadvantages of the device in the above described example, disappear. In place of these margins, there are an alignment margin 215 between a gate electrode wiring layer pattern 207 and the contact hole, and an alignment margin 216 between the gate electrode wiring layer 207 and a source/drain diffusion layer 209 constituting a transistor. These margins are sufficiently smaller than the margin 114 and margin 116 which are shown in FIG. 84(b). This can be seen from the following.
In this example, the first gate electrode wiring layer pattern serving as the electrode material of the floating gate in the memory cell transistor, which functions as the gate electrode in the peripheral transistor, and the second gate electrode wiring pattern serving as the electrode material of the control gate are different patterns, respectively, directly below the contact hole 113.
Non-volatile memories, such as NAND type flash memories, have a plurality of power supply voltages, such as a relatively high power supply voltage during write/erase operations, in addition to a power supply voltage during a reading operation. In order to select one of these power supplies during a desired operation, a resistive division is conventionally used. In order to realize this, a resistive element having a high resistance of about 1 Mxcexa9 is required in order to supply a stable power supply voltage. As a technique for forming such a resistive element, an electrode gate material of a floating gate having a relatively high resistance constituting a memory cell transistor is generally used. It is also considered that a control gate electrode material constituting a memory cell transistor and a diffusion layer resistance are used. In the former control gate electrode, a polycide structure of a metal having a high melting point is used as a relatively low resistance material necessary for cell operations. Therefore, a resistive element having a resistance of Mxcexa9 must be provided on the same substrate, so that a large forming region is required. On the other hand, when the latter diffusion layer resistance is used, it is possible to provide a relatively high resistance as compared with the control gate electrode material constituting the above described memory cell transistor. However, this can not be utilized as a stable resistive element since it has remarkable temperature characteristics. Therefore, a floating gate electrode material having a small fluctuation in resistance value due to temperature and a relatively high sheet resistance is widely used.
Thus, in the example shown in FIG. 84, if the floating gate electrode constituting the memory cell transistor is used as the gate electrode of the peripheral transistor, it is required to sufficiently ensure alignment margins relating to the formation of the contact hole in the floating gate electrode terminal, so that the area of the chip is increased.
It is therefore an object of the present invention to eliminate the aforementioned disadvantages and to provide measures to solve the problems.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; a plurality of first diffusion layers having a low impurity density, the first diffusion layers being formed on the surface of the semiconductor substrate; a plurality of second diffusion layers having a high impurity density, the second diffusion layers being formed on the surface of the semiconductor substrate; a plurality of first contacts, each of which contacts the first diffusion layers and each of which is formed of a semiconductor; and a plurality of second contacts, each of which contacts the second diffusion layers and each of which is formed of a metal.
According to another aspect of the present invention, there is provided a method for producing a semiconductor device having a semiconductor filled contact or a metal filled contact for a plurality of diffusion layers, the method comprising the steps of: forming a plurality of contact holes; filling a semiconductor in each of the first contact holes; carrying out a thermal treatment; forming a plurality of second contact holes; and filling a metal in each of the second contact holes.
According to another aspect of the present invention, there is provided a semiconductor device comprising: a memory cell part having a plurality of non-volatile memory cells, each of which has a floating gate electrode, a control gate and an insulating film arranged therebetween; a peripheral circuit having a plurality of peripheral transistors each having a gate electrode made of the material of the floating gate electrode; a plurality of cell gate contacts, each of which contacts a corresponding one of the control gate electrodes for activating a corresponding one of the memory cells; and a plurality of peripheral gate contacts, each of which contacts a corresponding one of the floating gate electrodes for activating a corresponding one of the peripheral circuits, each of the peripheral gate contacts being electrically connected to both of the corresponding one of the floating gate electrodes and the corresponding one of the control gate electrodes.
According to another aspect of the present invention, there is provided a method for producing a semiconductor device which comprises: a memory cell part having a plurality of non-volatile memory cells, each of which has a floating gate electrode, a control gate and an insulating film arranged therebetween; a peripheral circuit having a plurality of peripheral transistors each having a gate electrode made of the material of the floating gate electrode; a plurality of cell gate contacts, each of which contacts a corresponding one of the control gate electrodes for activating a corresponding one of the memory cells; and a plurality of peripheral gate contacts, each of which contacts a corresponding one of the floating gate electrodes for activating a corresponding one of the peripheral circuits, each of the peripheral gate contacts being electrically connected to both of the corresponding one of the floating gate electrodes and the corresponding one of the control gate electrodes, the method comprising the steps of:
simultaneously etching the floating gate electrodes and the insulating films to form contact holes; and
filling a contact material in the contact holes to form the peripheral gate contacts.
According to another aspect of the present invention, there is provided a semiconductor device comprising a memory cell array including memory transistors having a double-layer gate structure, and select gate transistors serving as gates for transmitting and receiving data to and from the memory transistors, wherein contacts with the gate electrodes of the select gate transistors are formed of a polysilicon.
According to another aspect of the present invention, there is provided a semiconductor high resistive element formed in a semiconductor substrate, in the substrate double-layer electrode type transistors are formed by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode,
wherein a pair of contact holes are formed in at least a material layer of the second gate electrode and a material layer of the second gate insulating film of the four layers at regular intervals, a wiring material is filled in each of the pair of contact holes so as to be electrically connected to a material layer of the first gate electrode, and an insulating material is arranged on an inner surface of each of the pair of contact holes to electrically isolate the wiring material from said material layer of the second gate electrode, so that the material layer of said first gate electrode is used as a resistive material.
According to another aspect of the present invention, there is provided a semiconductor high resistive element formed in a semiconductor substrate, in the substrate double-layer electrode type transistors are formed by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode,
wherein a pair of contact holes are formed in at least a material layer of the second gate electrode and a material layer of the second gate insulating film of the four layers at regular intervals, a wiring material is filled in each of the pair of contact holes so as to be electrically connected to a material layer of the first gate electrode, and the material layer of the second gate electrode is electrically cut at least one place between the pair of contact holes, so that the material layer of the first gate electrode is used as a resistive material.
According to a further aspect of the present invention, there is provided a method for producing a semiconductor element comprising a double-layer electrode type transistor formed on a semiconductor substrate by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode on the semiconductor substrate, the method comprising the steps of: forming an insulating film in a specific region on the semiconductor substrate; sequentially forming three layers of a material layer of the first gate electrode, a material layer of the second gate insulating film, and a material layer of the second gate electrode, on the insulating film; etching the material layer of the second gate electrode and the material layer of the gate insulating layer to form at least a pair of contact holes for exposing the material layer of the first gate electrode functioning as a resistive element material; selectively forming another insulating film on side walls of the contact holes; and filling a wiring material in the contact holes so that the wiring material is electrically insulated from the material layer of the second gate electrode by the another insulating film although the wiring material is electrically conducted to the material layer of the first gate electrode.
According to a still further aspect of the present invention, there is provided a method for producing a semiconductor element comprising a double-layer electrode type transistor formed on a semiconductor substrate by sequentially forming at least four layers of a first gate insulating film, a first gate electrode, a second gate insulating film and a second gate electrode on the semiconductor substrate, the method comprising the steps of: forming an insulating film in a specific region on the semiconductor substrate; sequentially forming three layers of a material layer of the first gate electrode, a material layer of the second gate insulating film, and a material layer of the second gate electrode, on the insulating film; etching, removing and cutting the material layer of the second gate electrode between a pair of contact hole intended regions to form a cut portion; etching the material layer of the second gate electrode and the material layer of the gate insulating layer to form at least a pair of contact holes for exposing the material layer of the first gate electrode functioning as a resistive element material; and filling a wiring material in the contact holes so that the wiring material is electrically conducted to the material layer of the first gate electrode.